C1008 FERA/NIM-ADC interface Users Manual

Important Notes On Use

1). An ADC must be connected to all units which are enabled for COINCIDENCE operation. If you fail to do this spurious operation (including hang ups) is likely. Unused units should simply be deselected in the setup software.

2) Ensure that the jumper and switch settings for the cards are correct for the type of ADC in use. Jumpers J1 to J37 are used to select the pin connections on the 37 way 'D' type ADC connector, i.e. the ADC signals used by the card. The default setting suits most common types of ADC. Additional links allow for up to 16 data inputs and differing signal pin connections. See Jumper connections (PS)

DATA13 = J13
DATA14 = J30
DATA15 = J31
DATA16 = J32

3)DIP switches SW1 and SW2 select the RAM address and SW3 and SW4 select the I/O address.

4) The terminator resistors must be removed from all boards in the readout chain except for the board furthest from the FERA controller card (e.g. C1009). The resistors should be stored in the appropriate positions RX3 to RX9 to the bottom right of the card. When re-installing the resistor packs in their working positions (RP3 to RP9) ensure that pin 1 (marked by a dot or symbol 1 on the resistor pack) is installed to the correct end of the connector.

RX3 => RP3    pin1 (dot) at top
RX4 => RP4    pin1 (dot) at top
RX5 => RP5    pin1 (dot) at bottom
RX6 => RP6    pin1 (dot) at bottom
RX7 => RP7    pin1 (dot) to right
RX8 => RP8    pin1 (dot) at top
RX9 => RP9    pin1 (dot) at top

5) VME address accesses are A32/D32 for the RAM and A16/D8 for I/O. The I/O addresses are all odd values (01,03,05 etc.).

6) On C1009 (FERA controller) the Jumpers select positive or negative NIM input configuration for a) VME GATE, b) FERA GATE and c) CLEAR.

C1008 ADC Interface Unit

a) RAM address (C1008 only)

	VME Range 		A32/D32

	Range			00000000 to FFFFFFFF

	RAM Size		40000 bytes

	e.g. of address	08000000 to 0803FFFF

	Set by switches SW1 and SW2

	SW2 	sw8	MSB 	A31		} Most significant nibble
		sw7		A30		}		"
		sw6		A29		}		"
		sw5		A28		}		"
	 	sw4	 	A27		} Next most significant nibble
		sw3		A26		} 		" 
		sw2		A25		}		"
		sw1	LSB	A24		}		"

	SW1 	sw6	MSB	A23		} Next most significant nibble
		sw5		A22		}		"
	 	sw4	 	A21		}		"
		sw3		A20		}		"
		sw2		A19		} Least significant nibble
		sw1	LSB	A18		}		"

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

b) I/O address

	VME Range 		A16/D8

	Range			0000 to FFFF

	Size			8 bytes on Odd addresses 
				(4 locations per board) 01,03,05 and 07
				or 09,0B,OD and 0F.

	e.g. of address	0810 to 0817 
		(uses addresses 0811,0813,0815 and 0817)

	Address Bits 15 14 13 12 11 10 9 8 .... main address
	Address Bits 7 6 5 4 3 .... sub address
	Set by switches SW4 and SW3 respectively

Main address block

	SW4 	sw8	MSB 	A15		} Most significant nibble
		sw7		A14		}		"
		sw6		A13		}		"
		sw5		A12		}		"
	 	sw4	 	A11		} Next most significant nibble	
		sw3		A10		} 		" 
		sw2		A09		}		"
		sw1	LSB	A08		}		"

Sub address block

	SW3 	sw6	MSB	A07		} Next most significant nibble
		sw5		A06		}		"
	 	sw4	 	A05		}		"
		sw3		A04		}		"
		sw2	LSB	A03		} Least significant nibble
		sw1		not used			

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

The I/O address is broken up into a main address block formed by the 8 MSB switches (SW4) and all ADC cards should have the same setting for one system (more than one data collection system may be installed in a crate, each system will have its own main address, common to all cards including its controller), and a sub address block for each card, set on SW3 which defines a card within the main address block.

The first address (xxx1 or xxx9) is common to all cards within the main address block set. This allows for a common ADC start/stop address for all cards in the same main address block. The controller card, if a type C1009, should also have the same main address block setting and it is suggested that it takes sub address block 0 (i.e. the first of the group).

Address decoding

	Address offset 1 (9)		Start/Stop register (common)		data on bit D0
	Address offset 3 (B)		Status/control Register			data=8 bits
	Address offset 5 (D)		Write VSN register			data=8 bits
	Address offset 7 (F)		Write DATA SIZE/MODE		data=3 bits
						(defaults to 12 bits and normal mode on PU)

Offset address 1 (or 9)

	Common to all ADC interface cards and control card (C1009) within main address block.

	Data bit D0 (only on C1008 cards):- 		D0=1....Singles RUN (if selected)
							D0=0....Singles HALT (if selected)

Offset address 3 (or B)

	Status (Read) and Control (Write) register, 8 bits as follows:-

	Control Register bits		Function
		0			Start RAM reset=1
		1			Select coincidence mode=1, singles free run=0
		2			Select singles mode=1, not selected=0
		3			No function
		4			Gate select bit 1
		5			Gate select bit 2
		6			General Reset
		7			No function

	Status Register bits		Function
		0			RAM reset under way=1, finished=0
		1			Coincidence mode=1, singles free run=0
		2			Singles mode=1, not selected=0
		3			Singles running=1, stopped=0 
						(0 always if not selected)
		4			Gate select bit 1
		5			Gate select bit 2
		6			No function (=0)
		7			ADC status (1=disabled or missing ADC)
						(0=ADC present and enabled)

	Gate control bits		bit 2		bit 1
	For NIM gate input		1		0
	For FERA gate input		0		1
	For VME gate input		1		1

Offset address 5 (or D)

	Write VSN value of 8 bits into VSN register. The VSN number has a unique value for each ADC, and is the first of two numbers read out on the FERA bus during data transfer from a coincidence event, it identifies from which ADC the data originated.

Offset address 7 (or F)

	Write an 3 bit value to DATA SIZE register. This value selects the width of the ADC data input. The power up default sets a value of 12 bits. Performing a second write of data value 0 (zero), after setting the data width (1 to 7), will switch the C1008 unit into MULTI-SPECTRA count mode. For further information on this please see the C1010 supplement to this manual.

	DATA SIZE 		data value written	
	10 bits			1
	11 bits			2
	12 bits			3 (default)
	13 bits			4
	14 bits			5
	15 bits			6
	16 bits			7

Examples of addresses

	Card 1		MAIN I/O Address	27 (hex)
	(Controller)	SUB I/O Address	00 (hex)

	Card 2	RAM Address	01040000-0107FFFF (256k)
			MAIN I/O Address	27 (hex)
			SUB I/O Address	08 (hex)

	Card 3	RAM Address	01080000-010BFFFF (256k)
			MAIN I/O Address	27 (hex)
			SUB I/O Address	10 (hex)

Data format

FERA header       1 0001 000 vvvvvvvv     (where vvvvvvvv = VSN)
FERA data word    0000 dddddddddddd       (for 12bit data word)

Front panel connectors and indicators (Top down)

	Termination LED		Terminator resistors installed when lit		

	Command bus		16 way IDC ribbon

	REN 			Readout Enable Input (Diff ECL)

	PASS			Enable Next Module out (Diff ECL)

	NIM GATE in		Lemo for separate -ve NIM input for gate

	GATE MONITOR		Monitor for the chosen gate signal TTL (not 50 ohm)

	VIEW MONITOR		Monitor for the RTP or VIEW from the ADC 
										(not 50ohm)

	ADC 37 way input	Main ADC data input - 37 way connector

	FERA Data output	FERA standard 16 bit data out (coinc mode) 
						(Diff ECL)


J Thornhill  16 May 1996.

Further information