C1009 VME/FERA ADC Controller

Operation and use

Operation

Operation criteria

An additional signal which is not standard for FERA readout is incorporated into the FERA command bus. Running along the front of the VME system, this is a second gate signal, VME-GATE used for coincidence mode operation as a coincidence trigger for the VME modules. The CAMAC FERA modules require a gate at a different time to the VME system and VME-GATE, used only for VME, allows for this. The VME interface cards are able to select from either the standard FERA GATE, VME-GATE or a front panel -ve NIM GATE input. Singles operation for any coincidence units, will be inhibited whenever the REQ line on the command bus is active, i.e. when a coincidence event (or CAMAC FERA unit) has valid data. Overall control of the interface coincidence HALT/GO is done over VME which in turn controls the CLEAR line on the FERA control bus. All VME singles units within one crate are started and stopped simultaneously by the same common VME I/O main address (be they in singles only mode or both coincidence and singles, but only if at the same main address).

Validation operation

Fig 1. Timing diagram for mixed VME and CAMAC system showing use of GATE 1 (FERA) and GATE 2 (VME).

Additional information on use

The singles histogram is 32 bits wide. The number of channels required being determined by the ADC resolution. The singles update speed is less than 500ns, plus any delay due to VME interlaced (transparent) reads. (Singles rates in excess of 1 million events per second are feasible). The VME card is a double height unit (6U) of single width VME(4HP) allowing at least 16 such units to be incorporated into one VME crate. Additional units may be placed into a second, third, forth etc. crate(s) as required, each crate requires a A32/D32 processor for control and singles readout. For coincidence readout all crates are connected into the one FERA bus controller, which may be in VME or FERA. All power comes from the +5v rail in the VME crate and on board DC-DC converters generate the required -5v.

Address switch settings

I/O address

	VME Range 			A16/D8

	Range				0000 to FFFF

	Size				8 bytes on Odd addresses 
					(4 locations per board) 01,03 and 05 
					or 09,0B and OD.

	e.g. of address 	0810 to 0817 (uses addresses 0811,0813 and 0815)

	Address Bits 15 14 13 12 11 10 9 8 .... main address
	Address Bits 7 6 5 4 3 .... sub address
	Set by switches SW2 and SW1 respectively

Main address block

	SW2 	sw8	MSB 	A15		} Most significant nibble
		sw7		A14		}		"
		sw6		A13		}		"
		sw5		A12		}		"
	 	sw4	 	A11		} Next most significant nibble	
		sw3		A10		} 		" 
		sw2		A09		}		"
		sw1	LSB	A08		}		"

Sub address block

	SW1 	sw6	MSB	A07		} Next most significant nibble
		sw5		A06		}		"
	 	sw4	 	A05		}		"
		sw3		A04		}		"
		sw2	LSB	A03		} Least significant nibble
		sw1		not used			

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

The I/O address is broken up into a main address block formed by the 8 MSB switches (SW2) and all ADC cards should have the same setting for one system as their controller. The sub address for the controller works in a similar way as for the ADC Interface units. The first address (xxx1 or xxx9) is common to all cards within the main address block set. This allows for a common ADC start/stop address for all cards in the same main address block. The it is suggested that the controller card takes sub address block 0 (i.e. the first of the group). The data bits D0 and D1 control the singles and coincidence data collection respectively. By writing 03 to the offset address 01 both the singles and coincidence data collection will start at the same time. Similarly 00 will halt both simultaneously.

Address decoding

	Address offset 1 (9)		Start/Stop coincidence register	data on bit D1
	Address offset 3 (B)		Write RESET DELAY register	data=8 bits
	Address offset 5 (D)		Write READOUT DELAY register	data=8 bits

Offset address 1 (or 9)

	Data bit D1 (only on C1009 cards):- 	D1=1....Coincidence RUN (if selected)
						D1=0....Coincidence HALT (if selected)

Offset address 3 (or B)

Offset address 5 (or D)

Additional information

Front panel connectors and indicators (Top down)

	Command bus		16 way IDC ribbon

	REQ 			Readout Enable Output (Diff ECL) [to REN]

	CLEAR IN		Clear input (Diff ECL) [from last module PASS] 

	WRITE STROBE OUT	Write strobe to memory unit (Diff ECL)

	WRITE ACK INPUT		Write acknowledge from memory unit (Diff ECL)

	INHIBIT INPUT		Inhibit data readout (Diff ECL)

	ROQ 			Readout Request Output to memory (Diff ECL)

	VME GATE in		Lemo for +/-ve NIM input for VME gate

	FERA GATE in		Lemo for +/-ve NIM input for FERA gate

	CLEAR in		Lemo for +/-ve NIM input for CLEAR

	WRITE ACK in		Lemo for -ve NIM input of WRITE ACK 

	REQUEST out		Lemo for -ve NIM output of READOUT REQUEST

	WRITE STROBE out	Lemo for -ve NIM output of WRITE STROBE

	Memory Data output	FERA standard 16 bit data out to memory 
						(Diff ECL)

	FERA DATA input		FERA standard 16 bit data input from bus 
						(single ended ECL)


	VME Singles - Coincidence FERA adc system

J Thornhill 18 August 1994.

Further information