C1010 VME/FERA TIMING Controller

The timer unit (C1010) consists of a complex PCB containing FPLA devices. The unit contains a timer/counter module, 4 x 64bit scalers, a VME interface and an interrupt controller. The timer/counter module is used for counting the periods defined by the user for each channel required. Up to 64 channels can be timed sequentially. The scalers count for each of the channel times specified and their counts are stored in RAM, separated into the individual time periods. The scalers have 4 individual inputs which accept positive NIM signals. (³+1.5V).

A VETO output is generated at the end of the last channel period and an interrupt is output onto VME if this function is enabled within the module. The VETO output may be used to halt external items ,e.g. any ADC, to stop further data collection.

Outputs are also provided (from 50ohm drivers) which connect to the COUNT, CLEAR and GND inputs on the C1008 cards (37way cannon pins 19,18 and 37 respectively). These outputs are available on LEMO connectors and also on the 9 pin Cannon plug on the front panel. The Cannon plug connections are as follows:-

	PIN		Function	Connect to PIN on C1008
	1		CLEAR		30
	2		gnd			36 (see note) 
	3		COUNT		32
	4		!VETO		n/c
	5		VETO		n/c
	6		gnd		-
	7		gnd		-
	8		gnd		-
	9		gnd		-

Note... any one of the 5 gnd pin connection can be used on the C1010 cannon plug.

Several jumpers are included on the C1010 card to control the clock selection, interrupt level and system reset enable. For the jumper positions please see the attached sheet. The jumpers perform the following functions:-

	J1		Hardware clock speed select (only if J2 set for hardware clock select).
				(2-1 = 100ms, 2-4 = 10ms, 2-3 = 1ms)
	J2		Hardware or software clock selection. (1-2 = software, 2-3 = hardware).
	J3		Connects SYS-RESET to board power-up reset line. (jumper fitted).
	J4		Ignore (no user function)

	I1 to I7	Interrupt level selected (1 through 7)   
	I0		Storage for jumper if no interrupt level required.
	IA1 to IA3	Interrupt acknowledge code (set to equal interrupt level) 
				Jumper fitted sets bit = 0, open = 1.

C1010 timer card

Operation

	1	off	64k	(10 to 16 bits by using the system as at present)
	8	off	8k	(13 bits)
	16	off	4k	(12 bits)
	32	off	2k	(11 bits)
	64	off	1k	(10 bits)

The smallest spectra size is 1k with 64 spectra possible. Options up to the maximum number of ADC spectra in each selection will be possible (e.g. 23 off 1k spectra, 3 off 4k spectra etc.).

ii). The spectrum number is contained in a counter on each ADC interface card, C1008. This reduces the complexity of the control unit (C1010) and avoids complex cable routing. The channel counters are reset and incrimented from the control unit (C1010) via a simple cable assembly and will only increment when the ADC connected to the C1008 unit is not busy. The time each spectra has allocated to it is determined by a table loaded into the control unit memory. The multi-spectra mode is entered on the C1008 card by first writing the data size to the DATA SIZE register and then writing zero to the same register. e.g. for a 12 bit ADC write the value 3 then 0. To change data size repeat the previous two writes with a new first value.

iii). A VETO (and !VETO) output is provided which is asserted at the end of the count time for the last channel. This output can be connected to the ADCs to halt data collection or to inform external units that the end of the last period has been reached. A status bit in the control unit will inform the VME processor of the end of data collection time. An interrupt controller is included into the VME interface in order to flag the completion to the processor. The processor would then halt data collection. (NOTE. An interrupt may not give sufficiently accurate timing to allow the data collection to be halted at a given time by using the processor alone, therefore the VETO connection on the front panel should also be used in this circumstance). Without using the VETO connection data will continue to be collected in the last selected spectra until a halt is issued. All the ADCs and the control unit respond to the same address broadcast to start and stop data collection, ensuring synchronism.

iv). The spectra increase from 0 to 1 to 2 etc. up to the desired number set by the user. All setup and control is from the VME interface.

v). Four scalers, each 64 bits wide are included in the design and again these are divided into channels with the same period timing as the ADCs. The scalers are read out over VME.

vi). It is possible to operate the system in singles or coincidence mode (multi-parameter) or any combination of the two modes. The coincidence data read out will also contain the spectra channel number.

Address switch settings

RAM address (C1010 only)

	VME Range 		A32/D16

	Range			00000000 to FFFFFFFF

	RAM Size		40000 bytes     (not all used)
				0 to 2k bytes read and write SCALER RAM
				2k to 4k bytes COUNTER RAM 
								(first 128 bytes used)

	e.g. of address	08000000 to 0803FFFF

	Set by switches SW1 and SW2

	SW2 	sw8	MSB 	A31		} Most significant nibble
		sw7		A30		}		"
		sw6		A29		}		"
		sw5		A28		}		"
	 	sw4	 	A27		} Next most significant nibble	
		sw3		A26		} 		" 
		sw2		A25		}		"
		sw1	LSB	A24		}		"

	SW1 	sw6	MSB	A23		} Next most significant nibble
		sw5		A22		}		"
	 	sw4	 	A21		}		"
		sw3		A20		}		"
		sw2		A19		} Least significant nibble
		sw1	LSB	A18		}		"

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

The SCALER RAM is located at the start of the address window from 0 upwards. It contains the counts from the scalers which have been stored in RAM, it is not possible to read directly from the scalers. The data from the scalers are stored in the RAM at the end of each time period set by the user. The RAM is cleared by writing 0 (16 bits) to the RAM over the VME bus. This can only be done when the system is HALTED.

The scalers are 64 bits wide and have +ve NIM inputs (>+1V into 1k). Maximum input voltage 20V.

The COUNTER RAM is located at the first 2k boundary within the address window and uses only the first 64 16bit locations (128 bytes). Data values can be written to and read from the RAM only when the system is HALTED. As many or as few locations are written to as required. The value written to the RAM is in the range 1 to 65535 which gives a count time of 1 to 65,535ms, 10 to 655,350ms or 100 to 6,553,500ms depending on the clock divisor selected.

I/O address

 
	VME Range 		A16/D8

	Range			0000 to FFFF
	Size			8 bytes on Odd addresses 
				(4 locations per board) 01,03,05 and 07
				or 09,0B,OD and 0F.

	e.g. of address	0810 to 0817 
	(uses addresses 0811,0813,0815 and 0817)

	Address Bits 15 14 13 12 11 10 9 8 .... main address
	Address Bits 7 6 5 4 3 .... sub address
	Set by switches SW4 and SW3 respectively

Main address block

	SW4 	sw8	MSB 	A15		} Most significant nibble
		sw7		A14		}		"
		sw6		A13		}		"
		sw5		A12		}		"
	 	sw4	 	A11		} Next most significant nibble	
		sw3		A10		} 		" 
		sw2		A09		}		"
		sw1	LSB	A08		}		"

Sub address block

	SW3 	sw6	MSB	A07		} Next most significant nibble
		sw5		A06		}		"
	 	sw4	 	A05		}		"
		sw3		A04		}		"
		sw2	LSB	A03		} Least significant nibble
		sw1		not used			

The I/O address is broken up into a main address block formed by the 8 MSB switches (SW2) and the timer unit should have the same setting for one system as the controller. The sub address for the timer works in a similar way as for the ADC Interface units. The first address (xxx1 or xxx9) is common to all cards within the main address block set. This allows for a common ADC/timer start/stop address for all cards in the same main address block. The data bits D0 and D1 control the singles and coincidence data collection respectively and bit D2 controls the run halt state of the c1010 timer unit. By writing 07 to the offset address 01 the singles, coincidence and timer unit will start at the same time. Similarly 00 will halt all simultaneously.

Address decoding

	Address offset 1 (9)		Start/Stop register (common)		data on bit D2
	Address offset 3 (B)		Status/control Register			data=8 bits
	Address offset 5 (D)		Channel count and CLK divisor	data=6+2 bits
	Address offset 7 (F)		Write Interrupt vector			data=8 bits

Offset address 1 (or 9)

	Data bit D2 (only on C1010 cards):- 	D2=1....Timer RUN
						D2=0....Timer HALT 

Offset address 3 (or B)

	Control Register bits		Function
		0    	(See NOTE)	Set CLEAR State, 1=clear set, 0=clear not set 
		1			No function
		2			No function
		3			Enable/Disable interrupt (1=enable, 0=disable)
		4			No function
		5			No function
		6			No function
		7			No function

	Status Register bits		Function
		0			CLEAR State, 1=clear set, 0=clear not set
		1			Stop latch, 1=End of last channel
		2			Run status, 0=halted, 1=running
		3			Enable/Disable interrupt status 0=disabled, 1=enabled
		4			No function (=0)
		5			No function (=0)
		6			No function (=0)
		7			No function (=0)

NOTE. When the CLEAR bit is set in the status register it (the CLEAR bit) will be cleared to 0 when a GO command is executed. This holds all internal circuits and external modules in the first channel before starting data collection. It is important that CLEAR must be asserted before data collection is started.

Offset address 5 (or D)

Range for CHANNEL COUNT is 1 to 64 for the equivalent number of channels (i.e. 0=1 channel, 5=6 channels, etc.) with 63 being a request for 64 channels. (i.e. value written to register is one less than number of channels required.)

The DATA SIZE register on the C1008 card must be set to a value in agreement with the maximum time periods you require. e.g. For a 12 bit ADC the maximum number of count periods is 16. For a 13 bit ADC the maximum is 8. ADCs of 14, 15 and 16 bits must use the 16 bit single period mode of the C1008.

The CLOCK DIVISOR bits (6 and 7) select the base period of the internal timer clock. This has values of 1ms, 10ms and 100ms.

	Data Bits	Value		Operation caused
	D0-D5		0-63		Channel count from 1 to 64 channels.
	D6-D7		0,1,2,3		1=10ms, 2=100ms, 3=1ms, (0=1ms, default).

Offset address 7 (or F)

J Thornhill 1996

Further information