C1011 VME Clock unit specification

The C1011 VME/FERA Event Tag counter and Scaler unit is an addition to the FERA/VME data collection system. The unit allows relative timing of events within the VME/FERA system to be recorded to 32 bit accuracy. Several different timescales are possible with an accurate clock selectable to be 100ns, 1us, 10us or 100us period. It uses FERA readout for the TAG counter value and will be read out every time a valid coincidence event occurs. If a coincidence event occurs with no ADC producing data then the unit will clear down after a programmable time unless the 'REQ output on' bit is selected in the status register in which case the unit will be read out for every gate received.

A 64 bit scaler that can be read out over VME is also included and has a separate negative nim input on the front panel. (This cannot be read from FERA).

The unit has 4 NIM gate inputs on the front panel as well as both the VME master gate and FERA master gate signals from the FERA control bus (on the 16 way IDC header). The source of the gate signal for the first two inputs is programmable and selected in the control register as follows:-

	input	a)	FERA master gate or NIM gate 1
	input	b)	VME master gate or NIM gate 2
	input	c)	NIM gate 3
	input	d)	NIM gate 4	

Fig 2. Diagram of gate input logic Operation.

The 4 inputs a,b,c and d are ORed to give an overall gate signal to indicate that an event has occurred, and a code is generated corresponding to the gate number which has been detected. The gate inputs are weighted so that input (a) is of highest priority and (d) lowest. This will prevent ambiguous codes in the readout header word should two gates arrive at the input simultaneously. In normal use the gates will be separated in time considerably. At this time a programmable counter is started that will cause the module to reset if a REQ signal is not detected on the FERA control bus before the reset counter reaches a user preset value. The reset counter has a full scale of approximately 50 us, and may be disabled by writing zero to it.

When readout occurs over the FERA bus the two bit code to indicate the source of the gate is read out together with the VSN number .

The value in the TAG counter is transferred to a holding register at the time of the first input gate detected and all other input gates are disabled. The unit will normally not generate a FERA readout REQ signal, unless otherwise requested by a control bit set from VME, as this would cause a readout to occur even if no ADC converted and generally this is undesirable.

If the C1011 unit has been enabled by the control bit set from the VME bus, it will intercept the REN and output its TAG counter data. If disabled the unit is ignored and REN is immediately passed to the PASS output.

The gates are re-enabled by the FERA clear signal on the FERA control bus, or by a timeout clear from within. The TAG counter can be reset to zero by a Fast clear input on the front panel of the unit or by a VME command. The counter will be reset to zero at the time of powering up.

The Tag counter has an ability to count at frequencies of 10 MHz, 1 MHz, 100 kHz and 10 kHz selectable by bits in the control register. The Tag counter is 32 bits wide and is read out over the FERA bus system as a 16 bit header followed by 2, 16 bit data words. The data words will be the value obtained from the TAG counter at the time of any one of the 4 gate inputs being driven. The header contains a preset VSN number (loaded over VME) and a 2 bit code identifying the source of the gate input. Logic on the card ensures that the counter value is latched only when the counter is stable. A LED is fitted to enable the user to observe readout cycles occurring from the unit. (Data valid or gate to readout clear time).

FERA format

       Fera header    100100ssvvvvvvvv           where ss = gate source (gate1=0 gate4=3)       
                                                 where vvvvvvvv = VSN
       Fera dataword  llllllllllllllll           lower 16bits of counter
       Fera dataword  uuuuuuuuuuuuuuuu           upper 16bits of counter

Address switch settings

RAM address (C1011)

	
	VME Range 		A32/D16

	Range			00000000 to FFFFFFFF

	Scaler Size		4  x  16 bit words at start of block.

	e.g. of address	08000000 to 0803FFFF

	Set by switches SW1 and SW2

	SW2 	sw8	MSB 	A31		} Most significant nibble
		sw7		A30		}		"
		sw6		A29		}		"
		sw5		A28		}		"
	 	sw4	 	A27		} Next most significant nibble	
		sw3		A26		} 		" 
		sw2		A25		}		"
		sw1	LSB	A24		}		"

	SW1 	sw6	MSB	A23		} Next most significant nibble
		sw5		A22		}		"
	 	sw4	 	A21		}		"
		sw3		A20		}		"
		sw2		A19		} Least significant nibble
		sw1	LSB	A18		}		"

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

I/O address

 
	VME Range 		A16/D8

	Range			0000 to FFFF

	Size			8 bytes on Odd addresses 
				(4 locations per board) 01,03,05 and 07
				or 09,0B,0D and 0F.

	e.g. of address	0810 to 0817 
	(uses addresses 0811,0813,0815 and 0817)

	Address Bits 15 14 13 12 11 10 9 8 .... main address
	Address Bits 7 6 5 4 3 .... sub address
	Set by switches SW4 and SW3 respectively

Main address block

	SW4 	sw8	MSB 	A15		} Most significant nibble
		sw7		A14		}		"
		sw6		A13		}		"
		sw5		A12		}		"
	 	sw4	 	A11		} Next most significant nibble 
		sw3		A10		} 		" 
		sw2		A09		}		"
		sw1	LSB	A08		}		"

Sub address block

	SW3 	sw6	MSB	A07		} Next most significant nibble
		sw5		A06		}		"
	 	sw4	 	A05		}		"
		sw3		A04		}		"
		sw2	LSB	A03		} Least significant nibble
		sw1		not used			

Memory map

I/O Registers

The VME registers appear as follows :-

	Address offset from base	Function (8 bit data)
		01 or 09		D1 start/stop, D3 enable/disable unit

		03 or 0B		status/control register

		05 or 0D		VSN number

		07 or 0F		Reset counter delay 
					(200 ns steps, 255 steps, 0=disabled)

Offset address 1 (or 9)

a) 	VME controlled (control register D5=1) where both the scaler and Tag counter system are started and stopped by coincidence start/stop commands (D1),
or 
b) 	Free running mode (control reg D5=0) where the state of D1 has no effect. 

For example, the unit may be disabled for FERA readout, D3=0, but the scaler could be started and stopped with D1=1/0. Here the Tag counter would not be read out and the module would be just acting as a scaler.

In normal use as a TAG counter both bits D1 and D3 would be written at the same time, and the control register bit D5 would be set to 1.

Offset address 3 (or B)

This gives access to the control and status registers of the unit.

	Control bits	Function
	D0		Gate 1 source 0=NIM1, 1=FERA Gate
	D1		Gate 2 source 0=NIM2, 1=VME Gate
	D2		REQ driven for FERA readout 1=Driven, 0=Not Driven
	D3		Fast Clear for TAG counter 1=Clear. (Reset pulsed on writing)
	D4		Clear scaler on reading 1=Enable, 0=Disable
	D5		SCA and TAG counter run MODE 0=Free run, 1=VME control (D1).
	D6		Tag clock divider bit A
	D7		Tag clock divider bit B

	Status bits	Function
	D0		Gate 1 source 0=NIM1, 1=FERA Gate
	D1		Gate 2 source 0=NIM2, 1=VME Gate
	D2		REQ driven for FERA readout 1=Driven, 0=Not Driven
	D3		FERA Readout enabled.
	D4		Scaler and TAG counter running.
	D5		SCA and Tag counter run MODE 0=Free run, 1=VME control
	D6		Tag clock divider bit A
	D7		Tag clock divider bit B

	Clock divider bits 	A	B	Frequency	Period
				0	0	10 MHz	        100ns
				1	0	1 MHz	        1us
				0	1	100 kHz	        10us
				1	1	10 kHz	        100us

Offset address 5 (or D)

Offset address 7 (or F)

Reading the Scaler

The scaler can be cleared by either writing to the scaler MSB address directly or, if control register bit D4 is set to 1, by reading from the MS word.

It is possible for the scaler to run in two different modes controlled by a control bit (D5) were the scaler will either free run or only run when coincidence data collection is enabled. (NOTE the D5 bit controls the TAG counter operation also).

The Power on default operation is to free run.

Jim Thornhill 8 November 1995

Further information