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Ultra Data Acquisition System

C1012 Quad ADC description

Specifications

Four independent successive-approximation ADCs with sliding scale linearisation, accepting analog input pulses in range 0 to +10v.

Independent singles histogramming into local 32bit memory.

Common dead-time coincidence mode.

Resolution: 3840 channels. Conversion time: 2.7 microSecs. Integral Non-linearity: < +/- 0.025% Differential Non-linearity: < +/- 1.0%

Lower level discriminator: 10 mV to 1V

Internal Readout: max 800 nsecs (max 200 nsecs per ADC)

FERA readout: 100 nsecs per word

Input circuits

The analogue input signal is applied directly to the input of the Peak Detector module. The input signal passes a threshold set (to be decided) on the input comparitor which in turn generates the ADCBUSY signal. The ADCBUSY in turn enables the ADC Clk FF to generate a convert pulse of ~60ns for the ADC module at the peak time of the input signal. ADCBUSY also triggers the start of the VIEW pulse (To be designed). The peak detector circuits are also enabled by the ADCBUSY signal (called !FREE). ADCs not enabled by the VME I/O to be used will have the ENABLE signal unset so that no ADCBUSY or !FREE is generated. The ADCBUSY FF is cleared by the !FECLEAR signal from the C1012ROC chip as required for singles or coincidence operation. The reset timing is discussed in the following sections.

ADCs in coincidence mode only.

In this case only ADCs enabled for coincidence will be operational. The input flow is as described in section 1. If the EXTGATE signal (FERA/VME gate) is overlapped by the end of the VIEW signal then the ADC is part of the coincidence event. If this is not the case and since the ADC is not in singles mode the ADC will convert but will not be read out. !FECLEAR will be asserted when the FERA CLI signal is received (COCLR in C1012ROC). If for some reason no ADCs in any module fall into the coincidence window (poor gating etc.) then the FERA CLI signal will not be generated. In this situation the ADCs should be cleared down by asserting an external FERA CLI signal to the C1009 input. See Note Below

NOTE:- Clearing a false coincidence event.

The CLI input to the C1009 could be generated in one of several ways. Firstly, by a gate and delay unit which is started by the gate and cleared with the FERA REQ. If no REQ is generated then after a time-out period the unit should produce a CLI signal. Secondly, if the FERA gate (FGATE) is used for the main ADC gate then the VME gate (VGATE) could be used to validate the event. In this case the REQ nim output on the C1009 should be connected to the VGATE nim input on the C1009. The validation timer on the C1009 should then be set to a time longer than the maximum conversion time after the gate, approximately 21ns minimum (16ns max VIEW time + 4us max ADC conversion + 1us ADC to coincidence FIFO). If in this case no REQ is received to validate the event (i.e. No ADC has data) then the ADCs are reset collectively. A third solution is to place a timer unit, C1011, in the FERA chain so that a REQ is generated for every coincidence gate.

Although it would have been possible to build separate timers on each ADC card this was not done since this would have caused non synchronous clearing of ADCs and possible data loss from following events.

ADCs in singles mode only.

In this case only ADCs enabled for singles will be operational. The input flow is as described in section 1. The ADC will convert and data will be read out into a FIFO controlled by the C1012ROC chip. The ADC will be reset as soon as data is transferred to the FIFO and since the ADC is not in coincidence mode will be available for new data as soon as !FECLEAR is removed at the end of the transfer of the data. The Singles data collection is enabled and disabled by a status bit in the VME interface and all cards with singles ADCs in use will be started and stopped simultaneously.

ADCs in singles and coincidence mode only.

ADCs are enabled for singles and coincidence operation by writting the correct value to the control register in the C1012ROC chip. The 8 data bits determine which ADCs are in singles and which in coincidence. (See documentation on VME interface later.) The ADC will accept data as described in section 1, then if the ADC has received a GATE signal overlapping the end of the VIEW the ADC will become part of the coincidence readout of this event. The C1012ROC will determine which ADCs have valid coincidence and singles data and transferres the data out to the coicidence and singles FIFOs as required. Any ADC with singles and not coincidence data will be read out after(normally) any coincidence ADC. An adc with singles and coincidence data will always have its singles and coincidence data read out at the same time. The !FECLEAR signal to reset the input stage of the ADC channel is generated by the CLI signal from the FERA bus. The singles readout does not generate a reset unless the ADC is not also in coincidence.

View and Threshold control

The VIEW and THRESHOLD for each ADC is set by the use of 3 toggle swithes, one SPST biased and two centre biased SPST switches. One switch selects which ADC is being adjusted, one sets threshold and one View. Both adjustments are up/down in operation. The switches will pulse EEPOTs which are from the Xicor range which have 32 discrete values. Theshold will be adjustable over 0 to 620mV in 20mV steps. View is adjustable in 0.5us steps to 15.5uS. These pots are from Sequoia Electronics Ltd on )01734 258 000. THESE ARE ALTERNATIVE METHODS TO BE CONSIDERED. For the prototype resistive elements (pots) will be used to prove the design. Alternative arrangements can be considered later.

VME Readout and Control

VME control to be similar to C1008 mapping, with 32 bit data reads of RAM data and 8 bit short I/O set-up. One register/address will select common features and which ADC is to be configured. A second register/address will carry ADC specific data. The VSN value will be contained in the same address as the C1008. RAM data will be accessed directly by address mapping for all ADCs.

Address switch settings

RAM address

	
	VME Address mode	A32/D32

	Address range		00000000 to FFFFFFFF

	RAM Size		65536 bytes

	e.g. address	08000000 to 0800FFFF

	Set by switches SW1 and SW2

	SW2 	sw8	MSB 	A31	} Most significant nibble
		sw7		A30	}		"
		sw6		A29	}		"
		sw5		A28	}		"
	 	sw4	 	A27	} Next most significant nibble
		sw3		A26	} 		" 
		sw2		A25	}		"
		sw1	LSB	A24	}		"

	SW1 	sw8	MSB	A23	} Next most significant nibble
		sw7		A22	}		"
	 	sw6	 	A21	}		"
		sw5		A20	}		"
		sw4		A19	} Least significant nibble
		sw3		A18	}		"
		sw2		A17	}		"
		sw1	LSB	A18	}		"

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

I/O address

	VME Address mode	A16/D8

	Address range		0000 to FFFF

	Size			8 bytes on Odd addresses 
				(4 locations per board)

	e.g. address	0810 to 0817 (uses addresses 0811,0813,0815 and 0817)

	Set by switches SW3 and SW4


Main address block

	SW4 	sw8	MSB 	A15	} Most significant nibble
		sw7		A14	}		"
		sw6		A13	}		"
		sw5		A12	}		"
		sw4	 	A11	} Next most significant nibble 
		sw3		A10	} 		" 
		sw2		A09	}		"
		sw1	LSB	A08	}		"


Sub address block

	SW3 	sw6	MSB	A07	} Next most significant nibble
		sw5		A06	}		"
		sw4	 	A05	}		"
		sw3		A04	}		"
		sw2	LSB	A03	} Least significant nibble
		sw1		not used

Switches set in the ON position (to the right) are logical 0. Switches in the OFF setting are logical 1 (to the left).

The I/O address is broken up into a main address block formed by the 8 MSB switches (SW4) and all ADC cards should have the same setting for one system (more than one data collection system may be intalled in a crate, each sytem will have its own main address common to all cards), and a sub address block for each card set on SW3 which defines a card within the main address block.

The first address (xxx1 or xxx9) is common to all cards within the main address block set. This allows for a common ADC start/stop address for all cards in the same main address block. The controler card, if a type C1009, should also have the same main address block setting and it is suggested that it takes sub address block 0 (i.e. the first).

Address offsets

The address offsets of 03,05,07 (and 0B,0D,0F) are all separate for each card, and are decoded as follows:-

	Address offset 01	Start/Stop register		data on bit D0,D1

	Address offset 03	Status/control Register	data=8 bits

	Address offset 05	Write VSN register		data=8 bits
		
	Address offset 07	Write sin/coinc select		data=8 bits

Offset address 1 (or 9)

Common to all ADC interface cards and control card (C1009) within main address block.

	Data bit D0 on C1012 cards:- 	D0=1....Singles RUN (if selected)
						D0=0....Singles HALT (if selected)
	Data bit D1 on C1012 cards:- 	D1=1....Coincidence RUN (if selected)
						D1=0.... Coincidence HALT (if selected)

Offset address 3 (or B)

Status (Read) register, 8 bits as follows:-

	D0	Singles Mode Selected=1
	D1	Coincidence Mode Selected=1
	D2	Sliding Scale set to ZERO=1
	D3	Sliding Scale set to FULL SCALE=1
	D4	Gate Select bit 1=VME, 0=FERA
	D5	not used(0)
	D6	not used(0)
	D7	Ram Reset Under way=1

Control (Write) register, 8 bits as follows:-

	D0	ADC No. to be reset (RD0) see table below
	D1	ADC No. to be reset (RD1) see table below
	D2	Sliding Scale Mode bit 0 (SSD0) see table below
	D3	Sliding Scale Mode bit 1 (SSD1) see table below
	D4	Gate source select 1=VME, 0=FERA
	D5	no function
	D6	Master RESET
	D7	Ram Reset start (Must inclde ADC No. Data on bits D0 and D1)


ADC Reset codes		RD1	RD0		ADC No.
	0	0	1
	0	1	2
	1	0	3
	1	1	4			

Sliding Scale mode codes	SSD1	SSD0			MODE.
	0	0	SS  ON (DEFAULT)
	0	1	SS SET TO ZERO
	1	0	SS SET TO FULL
	1	1	SS ON (AS [0,0])

Offset address 5 (or D)

Write VSN value of 8 bits into VSN register. The VSN number has a unique value for each ADC, and is the first of two numbers read out on the FERA bus during data transfer from a coincidence event, it identifies from which ADC the data originated.

Offset address 7 (or F)

Write an 8 bit value to ADC Singles and/or Coincidence Select Register. This value selects which ADCs will be set into either singles and/or coincidence mode or neither. The lower 4 bits (D0-D3) set the COINCIDENCE ADCs either ON or OFF. The top 4 bits (D4-D7) set the SINGLES ADCs either ON or OFF. As Follows:-

	D0	ADC1 Coincidence ON=1, OFF=0
	D1	ADC2 Coincidence ON=1, OFF=0
	D2	ADC3 Coincidence ON=1, OFF=0
	D3	ADC4 Coincidence ON=1, OFF=0
	D4	ADC1 Singles ON=1, OFF=0
	D5	ADC2 Singles ON=1, OFF=0
	D6	ADC3 Singles ON=1, OFF=0
	D7	ADC4 Singles ON=1, OFF=0

Data format

This board outputs one to four data words per FERA header.

FERA header       1 nnnn 000 vvvvvvvv     (where nnnn = word count)
                                          (where vvvvvvvv = VSN)
FERA data word    0 ss 0 dddddddddddd     (for 12bit data word)
                                          (where ss= sub-address)

N.B. Position of sub-address field makes it compatible with quad ADC (13 bit) FERA modules.

Further information

Please contact jrc@ns.ph.liv.ac.uk

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Last modified: 8 January 1998

Maintained by John Cresswell, jrc@ns.ph.liv.ac.uk